1. Field of the Invention
The present invention relates to a lateral power MOSFET adopted for intelligent power ICs, smart power ICs, and vehicle ICs, and particularly, to a lateral power MOSFET having low ON resistance.
2. Description of the Prior Art
Power MOSFETs are widely used because they are easy to drive and have a high switching speed compared with bipolar transistors. Their ON resistance and operation speed, however, must be further improved. Lateral power MOSFETs have been briskly developed and marketed as elements of power ICs for driving the actuators of motors and coils for office and factory automation equipment, information equipment, vehicles, household electric equipment, etc. The power ICs are actively used because they are controllable with a compact controller, can be installed in a motor, and cooperate with intelligent detectors and protection circuits. To Integrate PWM controllers and three-phase bridge circuits for controlling a motor, the lateral power MOSFETs are advantageous because they are capable of providing multiple outputs. To fabricate a plurality of output transistors in a chip, the lateral power MOSFETs are advantageous because their source electrodes, gate electrodes, and drain electrodes are on the same principal plane.
The most important factor of the power MOSFET is ON resistance R.sub.ON. FIGS. 1A and 1B show a lateral power MOSFET of 50 V in breakdown voltage disclosed in Japanese Laid-Open Patent Publication No. 3-257969. This MOSFET has a p base region 5 and an n.sup.+ source region 6 that are formed by double diffusion of impurities. This MOSFET is called a double-diffused MOSFET (DMOSFET), and a lateral DMOSFET is called an LDMOSFET.
FIG. 1A is a sectional view and FIG. 1B is a plan view showing the LDMOSFET. In FIG. 1A, an n.sup.+ buried layer 2 is formed in a principle plane of a p substrate 1, a p epitaxial layer 3 is formed on the same principle plane, and n drain regions 4 are formed as n wells in the p epitaxial layer 3. LDMOSFETs are formed in the n wells, respectively, to operate independently of one another. In each of the n drain regions 4, p base regions 5 and n.sup.30 drain regions 8 are formed. In each of the p base regions 5, an n.sup.+ source region 6 is formed. A gate insulation film 9 is formed on the entire surface of the n drain regions 4, and a gate electrode 10 is formed on the gate insulation film 9, to partly cover the n drain region 4 between the adjacent p base regions 5 as well as the p base regions 5. A first insulation interlayer 11 is formed over the gate electrode 10, and a source electrode 12 and a first drain electrode 13 are formed on the first insulation interlayer 11. A second insulation interlayer 14 is formed over the source electrode 12, and a second drain electrode 15 is formed on the second insulation interlayer 14. In FIG. 1B, six source cell regions S are arranged in a hexagon pattern around a drain cell region D.
According to this prior art, the source electrode 12 and second drain electrode 15 form a double layer structure, to form source and drain openings as cells. The hexagonal pattern of source cell regions S is advantageous to integrate the elements and reduce the ON resistance R.sub.ON of the LDMOSFET to some extent.
The ratio of the source cell regions S to the drain cell regions D of the prior art is 2:1 as shown in FIG. 1B, to hardly reduce channel resistance. Namely, this prior art is incapable of sufficiently reducing the ON resistance. It is required, therefore, to provide a technique of further reducing the ON resistance.